Bridge hub tiling architecture

ABSTRACT

Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/857,752, filed on Dec. 29, 2017, the entire contents of which ishereby incorporated by reference herein.

TECHNICAL FIELD

The present disclosure relates to semiconductor packaging.

BACKGROUND

Next-generation data centers are trending toward systems providinggreater computational capabilities, operational flexibility, andimproved power efficiency. The combination of demands presented bynext-generation data centers present significant challenges for currentgeneral-purpose servers. Increasing demand for reduced system complexityand business agility and scalability has increased demand forvirtualized data center infrastructure will place additional demands onnext-generation data servers. To meet such varied requirements,next-generation servers may be designed to address a specific workloadmatrix. However, such task- or service-oriented design, while improvingpower efficiency, compromises the long term flexibility of suchnext-generation servers. Thus, the servers used in next-generation datacenters must be capable of providing a cost effective solution thataddresses current and future computational demands, provides a flexibleplatform capable of meeting evolving operational needs, while deliveringimproved power efficiency over legacy servers.

The challenges presented by the growing ubiquity of Internet-of-Things(IoT) devices are surprisingly similar to those presented bynext-generation data centers. With literally billions of connecteddevices, cloud-based infrastructure must quickly evaluate high-bandwidthdata streams and determine which data may be processed and which datamay be safely dropped.

Next-generation platforms share several distinct requirements: increasedbandwidth; increased flexibility to promote increased functionality;improved power efficiency (or reduced power consumption) and reducedfootprint requirements. Heretofore, designers may address such varieddemands by packing additional components on a standard printed circuitboard. The limitations inherent in such single board solutions may notsatisfactorily address the multiple demands placed on next-generationdevices. Such limitations include: chip-to-chip bandwidth limitationsbased on interconnect density; the power demand of long distance tracesbetween chips; and the increased physical size of printed circuit boardsto accommodate the chips. Monolithic integration of system componentsprovides a potential solution, however such integration does not readilypermit the integration of system components, each of which may evolve atdifferent rates. For example, a logic chip built using a newertechnology may not easily integrate or lend itself to monolithicfabrication with a memory chip built using an older technology.

Conventional solutions are therefore unable to meet future demands ofhigher bandwidth, greater power efficiency, increased functionality, andincreased operational flexibility—all in a physically smaller package.

BRIEF DESCRIPTION OF THE DRAWINGS

Features and advantages of various embodiments of the claimed subjectmatter will become apparent as the following Detailed Descriptionproceeds, and upon reference to the Drawings, wherein like numeralsdesignate like parts, and in which:

FIG. 1A is a schematic of an illustrative system that includes at leastthree semiconductor dies each of the semiconductor dies conductivelycoupled to the remaining semiconductor dies using an multi-dieinterconnect bridge at least partially disposed in the semiconductorpackage substrate, in accordance with at least one embodiment describedherein;

FIG. 1B is a cross-sectional elevation of the illustrative systemdepicted in FIG. 1A along section line 1B-1B, in accordance with atleast one embodiment described herein;

FIG. 2A is a plan view of an illustrative semiconductor package 200 thatincludes four semiconductor dies, each having a respective PHY layertransceiver conductively coupled to a single, centrally located,multi-die interconnect bridge, in accordance with at least oneembodiment described herein;

FIG. 2B is a schematic view of the communication pathways provided bythe single, centrally located, multi-die interconnect bridge as depictedin FIG. 2A, in accordance with at least one embodiment described herein;

FIG. 3 is a plan view of a system that includes a semiconductor packagein which a total of nine semiconductor dies are communicably coupledtogether using only four multi-die interconnect bridges, in accordancewith at least one embodiment described herein;

FIG. 4 is a plan view of a system that includes a semiconductor packagein which a total of sixteen semiconductor dies are communicably coupledtogether using only five multi-die interconnect bridges, in accordancewith at least one embodiment described herein;

FIG. 5A is a plan view of an illustrative semiconductor package having afirst non-conventional configuration that includes three rectangularsemiconductor dies conductively coupled to a single, triangular,multi-die interconnect bridge, in accordance with at least oneembodiment described herein;

FIG. 5B is a plan view of an illustrative semiconductor package having asecond non-conventional configuration that includes four rectangularsemiconductor dies conductively coupled to a single, cruciform,multi-die interconnect bridge, in accordance with at least oneembodiment described herein;

FIG. 5C is a plan view of an illustrative semiconductor package having athird non-conventional configuration that includes three triangularsemiconductor dies conductively coupled to a single, triangular,multi-die interconnect bridge, in accordance with at least oneembodiment described herein;

FIG. 5D is a plan view of an illustrative semiconductor package having afourth non-conventional configuration that includes six triangularsemiconductor dies conductively coupled to a single hexagonal multi-dieinterconnect bridge, in accordance with at least one embodimentdescribed herein;

FIG. 5E is a plan view of an illustrative semiconductor package having afifth non-conventional configuration that includes four semiconductordies conductively coupled to a single cruciform multi-die interconnectbridge, in accordance with at least one embodiment described herein;

FIG. 6A is a plan view of an illustrative system that includes asemiconductor package in which a single multi-die interconnect bridgethat includes an active die conductively couples four semiconductordies, in accordance with at least one embodiment described herein;

FIG. 6B is a cross sectional elevation of the illustrative semiconductorpackage depicted in FIG. 6A along section line 6B-6B, in accordance withat least one embodiment described herein;

FIG. 7 is a schematic diagram of an illustrative electronic device thatincludes a system-in-chip (SiC) that includes a multi-die interconnectbridge as described in FIGS. 1 through 6 conductively coupling agraphical processing unit, processor circuitry, and system memory, andin accordance with at least one embodiment described herein;

FIG. 8 is a high-level flow diagram of an illustrative method offabricating a semiconductor package, such as a system-in-chip, thatincorporates at least one multi-die interconnect bridge thatcommunicably couples at least three semiconductor dies, in accordancewith at least one embodiment described herein; and

FIG. 9 is a high-level flow diagram of an illustrative method ofconductively coupling one or more active dies to a passive multi-dieinterconnect bridge, in accordance with at least one embodimentdescribed herein.

Although the following Detailed Description will proceed with referencebeing made to illustrative embodiments, many alternatives, modificationsand variations thereof will be apparent to those skilled in the art.

DETAILED DESCRIPTION

The systems and methods described herein facilitate the coupling ofvarious semiconductor dies (“chiplets”) within a semiconductor packageusing a multi-die interconnect bridge disposed in the surface of thesemiconductor package substrate and communicably couples three or moresemiconductor dies such that each of the three or more semiconductordies is conductively coupled to each of the remaining three or moresemiconductor dies and the conductive coupling between any two of the atleast three semiconductor dies does not pass through any othersemiconductor die included in the at least three semiconductor dies. Themulti-die interconnect bridge may be formed as a separate silicon diethat is at least partially embedded in the semiconductor packagesubstrate during the package fabrication process. The multi-dieinterconnect bridge may be formed integral with the semiconductorpackage substrate during the substrate fabrication process. Each of theat least three semiconductor dies conductively coupled to the multi-dieinterconnect bridge may occupy the same or differing physical areas onthe surface of the semiconductor package substrate. The multi-dieinterconnect bridge may occupy a physical area of the surface of thesemiconductor package substrate that is less than the physicallysmallest of the at least three semiconductor dies.

The use of multi-die interconnect bridges to conductively couple atleast three semiconductor dies occupy a minimal footprint on thesemiconductor package substrate, permitting greater density andconsequently a reduced package footprint. Physical proximity of theconstituent semiconductor dies coupled to the bridge shortens theinterconnect length, beneficially improving bandwidth and powerefficiency. The use of multi-die interconnect bridges to conductivelycouple at least three semiconductor dies does not require the use ofthrough silicon vias (TSVs), beneficially improving signal quality andbandwidth when compared to traditional silicon interposer layers. Theuse of multi-die interconnect bridges to conductively couple at leastthree semiconductor dies permits the selective use of fine-pitchmicro-bumps for high density communications and coarser-pitch flip-chipbumps for power and ground connections.

The multi-die interconnect bridge may include only conductors todirectly couple each of the at least three semiconductor dies to theremaining at least three semiconductor dies. The multi-die interconnectbridge may include one or more active elements, such as controlcircuitry and/or repeater circuitry between one or more of the at leastthree semiconductor dies and the remaining at least three semiconductordies.

The use of an multi-die interconnect bridge also decouples each of theat least three semiconductor dies, permitting the use of mixedarchitecture dies in a single package—something that is not possibleusing monolithic manufacturing techniques. For example, the use of anmulti-die interconnect bridge permits the operable and conductivecoupling of a logic chip manufactured using 14 nanometer (nm) technologyto a memory chip manufactured using 40 nm technology and a graphicsprocessing unit (GPU) manufactured using 28 nm technology. Thus,individual semiconductor die components may be mixed and matched asneeded to provide a flexible system architecture that meets energy andperformance criteria.

When compared to physically larger silicon interposers, the smallermulti-die interconnect bridge is generally less expensive and less proneto manufacturing issues such as warpage. Further, for each signal thatconnects to a ball coupled to the semiconductor package substrate, asilicon interposer requires a corresponding through silicon via (TSV).Such TSVs add to package manufacturing complexity. The increase inmanufacturing complexity increased incremental yield loss, adverselyimpacting overall commercial viability. Additionally, the use of a largenumber of TSVs results in poor signal integrity for high-speed signalsand causes IR drop for power delivery nets. TSVs also add seriesresistance and capacitance which impair high speed design fortransceiver blocks on the semiconductor dies.

A semiconductor package is provided. The semiconductor package mayinclude: a semiconductor package substrate having a first surface and atransversely opposed second surface separated by a thickness; at leastthree semiconductor dies coupled to the semiconductor package substrate;where a smallest of the at least three semiconductor dies occupies afirst physical area on the first surface of the semiconductor packagesubstrate; and

a multi-die interconnect bridge that includes one or more conductivemembers disposed proximate the first surface of the semiconductorpackage substrate and occupying a second physical area of the firstsurface of the semiconductor package substrate; wherein the multi-dieinterconnect bridge conductively couples each of the at least threesemiconductor dies to each of the remaining at least three semiconductordies; and wherein the second physical area occupied by the multi-dieinterconnect bridge is less than the first physical area of a smallestof the at least three semiconductor dies.

A semiconductor package fabrication method is provided. The method mayinclude: disposing a multi-die interconnect bridge that includes aplurality of conductive members proximate a first surface of asemiconductor package substrate, the multi-die interconnect bridgeoccupying a first physical area of the first surface of thesemiconductor package substrate; and

conductively coupling each of at least three semiconductor dies to themulti-die interconnect bridge such that the plurality of conductivemembers conductively couples each of the at least three semiconductordies to the remaining at least three semiconductor dies; where asmallest of the at least three semiconductor dies occupies a secondphysical area on the first surface of the semiconductor packagesubstrate; and where the first physical area occupied by the multi-dieinterconnect bridge is less than the second physical area of a smallestof the at least three semiconductor dies.

A semiconductor package fabrication system is provided. Thesemiconductor package fabrication system may include: means fordisposing a multi-die interconnect bridge that includes a plurality ofconductive members proximate a first surface of a semiconductor packagesubstrate, the multi-die interconnect bridge occupying a first physicalarea of the first surface of the semiconductor package substrate; andmeans for conductively coupling each of at least three semiconductordies to the multi-die interconnect bridge such that the plurality ofconductive members conductively couples each of the at least threesemiconductor dies to the remaining at least three semiconductor dies;where a smallest of the at least three semiconductor dies occupies asecond physical area on the first surface of the semiconductor packagesubstrate; and where the first physical area occupied by the multi-dieinterconnect bridge is less than the second physical area of a smallestof the at least three semiconductor dies.

An electronic device that includes a semiconductor package having atleast one multi-die interconnect bridge is provided. The electronicdevice may include: a printed circuit board; a semiconductor packageconductively coupled to the printed circuit board, the semiconductorpackage including: a semiconductor package substrate coupled to theprinted circuit board, the semiconductor package substrate having afirst surface and a transversely opposed second surface separated by athickness; at least three semiconductor dies included in thesemiconductor package and coupled to the first surface of thesemiconductor package substrate; where a smallest of the at least threesemiconductor dies occupies a first physical area on the first surfaceof the semiconductor package substrate; and a multi-die interconnectbridge disposed proximate the first surface of the semiconductor packagesubstrate, the multi-die interconnect bridge including one or moreconductive members and occupying a second physical area of the firstsurface of the semiconductor package substrate; where the multi-dieinterconnect bridge conductively couples each of the at least threesemiconductor dies to each of the remaining at least three semiconductordies; and where the second physical area occupied by the multi-dieinterconnect bridge is less than the first physical area of a smallestof the at least three semiconductor dies.

As used herein the terms “top,” “bottom,” “upper,” “lower,” “lowermost,”and “uppermost” when used in relationship to one or more elements areintended to convey a relative rather than absolute physicalconfiguration. Thus, an element described as an “upper film layer” or a“top element” in a device may instead form the “lowermost element” or“bottom element” in the device when the device is inverted. Similarly,an element described as the “lowermost element” or “bottom element” inthe device may instead form the “uppermost element” or “top element” inthe device when the device is inverted.

As used herein, the term “logically associated” when used in referenceto a number of objects, systems, or elements, is intended to convey theexistence of a relationship between the objects, systems, or elementssuch that access to one object, system, or element exposes the remainingobjects, systems, or elements having a “logical association” with or tothe accessed object, system, or element. An example “logicalassociation” exists between relational databases where access to anelement in a first database may provide information and/or data from oneor more elements in a number of additional databases, each having anidentified relationship to the accessed element. In another example, if“A” is logically associated with “B,” accessing “A” will expose orotherwise draw information and/or data from “B,” and vice-versa.

FIG. 1A is a schematic of an illustrative system 100 that includes atleast three semiconductor dies 110A-110D (collectively, “semiconductordies 110”) each of the semiconductor dies conductively coupled to theremaining semiconductor dies using an multi-die interconnect bridge 120at least partially disposed in the semiconductor package substrate 130,in accordance with at least one embodiment described herein. FIG. 1B isa cross-sectional elevation of the illustrative system 100 depicted inFIG. 1A along section line 1B-1B, in accordance with at least oneembodiment described herein. In embodiments, the semiconductor package102 may be conductively coupled to a substrate 140, such as a circuitboard or similar. In embodiments, the multi-die interconnect bridge 120may include a silicon die that fabricated separate from thesemiconductor package substrate 130 and is at least partially embeddedin a first surface 132 of the semiconductor package substrate 130. Inother embodiments, the multi-die interconnect bridge 120 may befabricated integral with the semiconductor package substrate 130.

The multi-die interconnect bridge 120 provides a bidirectionalcommunication path 122A-122 n (collectively, “communication paths 122”)between each of the at least three semiconductor dies 110 and some orall of the remaining at least three semiconductor dies 110.Beneficially, the bidirectional communication paths 122 between anysemiconductor dies 110 conductively coupled to the multi-dieinterconnect bridge 120 occurs without passing through any interveningdies included in the at least three semiconductor dies 110. Inembodiments, the multi-die interconnect bridge 120 defines the shortestcommunication path 122 between any two of the at least threesemiconductor dies 110. By providing the shortest, direct,communications path 122 between each of the at least three semiconductordies 110 coupled to the multi-die interconnect bridge 120, power loss isreduced, power efficiency is increased, and communication bandwidth ismaximized.

The semiconductor dies 110 may include any number, combination, and/ortype of currently available and/or future developed dies. Examplesemiconductor dies 110 include, but are not limited to one or more:central processing units (CPUs); application specific integratedcircuits (ASICs); field programmable gate arrays (FPGAs); transceivers;flash memories; dynamic random access memories (DRAMs); and similar. Inembodiments, the semiconductor dies 110 may form a system-in-package(SiP) semiconductor package 102. In embodiments, the semiconductor dies110 disposed on the semiconductor package substrate 130 may integratechiplets or semiconductor dies 110 from different process nodes in asingle package. For example, in contrast to monolithic semiconductorpackage architecture, the systems and methods described herein permitthe integration of semiconductor dies 110 having differing architectures(14 nanometer, 20 nanometer, 28 nanometer, and 40 nanometer, etc.) in asingle semiconductor package 102.

The ability to quickly and efficiently change the semiconductor dies 110included in a semiconductor package 102 beneficially improvesmanufacturing flexibility and market responsiveness. For example, asemiconductor package 102 manufactured for a first customer may includeone or more Peripheral Component Interconnect Express (PCIe) Gen 3transceivers while a second customer requires the same semiconductorpackage 102 with a one or more semiconductor dies 110 optical and/orPulse Amplitude Modulated (e.g., PAM-4) transceivers. Sincesemiconductor dies 110 may be readily substituted without requiring acomplete rework of the semiconductor package 102, time-to-market isreduced and market responsiveness beneficially improved. Similarly,incremental improvements in technology (e.g., 3G to 4G to 5Gimprovements in cellular communications technology) may be readilyincorporated into a semiconductor package 102 without requiring a costlyand time-consuming redesign of the entire package.

Each of the at least three semiconductor dies 110 includes any number ofcontact elements 112A-112 n (lands, pads, grooves, pins, sockets,etc.—collectively “contact elements 112”) disposed in, on, about, oracross at least a portion of the lower surface of the semiconductor die110. In embodiments, the semiconductor dies 110 may communicably coupleto the multi-die interconnect bridge 120 using relatively smallconductive structures 154A-154 n (collectively, “conductive structures154”), such as micro-bumps compatible with a fine-pitch and/orhigh-density connection configuration. In some embodiments, suchhigh-density connections may be used for inter-die communication betweensome or all of the at least three semiconductor dies 110 coupled to themulti-die interconnect bridge 120. In embodiments, the semiconductordies 110 may communicably couple to the multi-die interconnect bridge120 using relatively large conductive structures 152A-152 n(collectively, “conductive structures 152”), such as solder ballcompatible with a relatively coarse-pitch and/or relatively low densityconnection configuration. In such embodiments, low-density connectionsmay be useful as inter-die power distribution and/or grounding betweensome or all of the at least three semiconductor dies 110 coupled to themulti-die interconnect bridge 120.

In embodiments, some or all of the at least three semiconductor dies 110may be manufactured using a flip-chip manufacturing technique in whichcircuitry is formed in each die on a wafer, metallized pads are formedon the wafer, conductive structures 152 and/or conductive structures 154are deposited, patterned, positioned, or otherwise formed on themetallized pads, and the wafer is singulated to form semiconductor dies110. The singulated semiconductor dies 110 are positioned on thesemiconductor package substrate 102 and/or the multi-die interconnectbridge 120 and the conductive structures 152 and/or conductivestructures 154 reflowed to physically attach and conductively bond theat least three semiconductor dies 110 to the multi-die interconnectbridge 120 and to the semiconductor package substrate 102.

The use of a central multi-die interconnect bridge 120 to conductivelycouple the at least three semiconductor dies 110 may reduce the numberof transceivers patterned or otherwise formed in, on, or about each ofthe at least three semiconductor dies 110. For example, in aconventional layout, an multi-die interconnect bridge is used to connecttwo die-to-die transceivers patterned or otherwise formed in adjacentsemiconductor dies. Thus, a square semiconductor die surrounded by fourother semiconductor dies (one on each side) may require up to four (4)different die-to-die transceivers, one for each multi-die interconnectbridge. The systems and methods described herein reduce the requirednumber of transceivers on each of the to one, freeing the die areapreviously occupied by three (3) additional die-to-die transceivers.

In embodiments, each of the at least three semiconductor dies 110 occupya defined area on an upper or first surface 132 of the semiconductorpackage substrate 130. Each of the at least three semiconductor dies 110may occupy the same or differing areas on the first surface 132 of thesemiconductor package substrate 130. At least one of the at least threesemiconductor dies 110 may occupy less surface area on the first surface132 of the semiconductor package substrate 130 than the remaining atleast three semiconductor dies 110. Thus, the at least one of the atleast three semiconductor dies 110 occupying the least surface area ofthe first surface 132 of the semiconductor package substrate may beconsidered the “smallest” of the at least three semiconductor dies 110.

The multi-die interconnect bridge 120 conductively couples each of theat least three semiconductor dies 110 to each of the remaining at leastthree semiconductor dies using contact elements 124A-124 n (lands, pads,grooves, pins, sockets, etc.—collectively, “contact elements 124”)disposed in, on, about, or across at least a portion of an upper surfaceof the multi-die interconnect bridge 120. In embodiments, the multi-dieinterconnect bridge 120 may be fabricated as a silicon die that is atleast partially deposited, sunken, or otherwise embedded into the firstsurface 132 of the semiconductor package substrate 130 during substratefabrication. In other embodiments, the multi-die interconnect bridge 120may be integrally fabricated in the first surface 132 of thesemiconductor package substrate 120. In yet other embodiments, themulti-die interconnect bridge 120 may include a silicon member that iselectrically isolated from the semiconductor package substrate 130 anddisposed proximate the first surface 132 of the semiconductor packagesubstrate 130.

The multi-die interconnect bridge 120 may include any number ofconductive members (traces, elements, wires, conductors, etc.) thatprovide any number of communications paths 122A-122 n between at leastsome of the at least three semiconductor dies 110A-110 n. The conductivemembers forming the communications paths 122 may be formed, patterned,deposited or otherwise arranged in any number of layers or similarstructures. Further, the multi-die interconnect bridge 120 includes anynumber and/or combination of contact elements 124A-124 n (lands, pads,grooves, sockets, etc.—collectively, “contact elements 124”) thatconductively couple to the at least three semiconductor dies 110. Themulti-die interconnect bridge 120 may have any physical geometry, size,and/or shape suitable for physical and conductive coupling to the atleast three semiconductor dies 110. For example, the multi-dieinterconnect bridge 120 may have a square, rectangular, triangular,circular, oval, or multi-sided polygonal configuration. As depicted inFIGS. 1A and 1B, the multi-die interconnect bridge 120 includes a numberof relatively short communication paths 122 that conductively couplessemiconductor die 110A with each of some or all of the remainingsemiconductor dies 110B-110D. In embodiments, the communication paths122 may define the shortest distance between any two of the at leastthree semiconductor dies 110.

The multi-die interconnect bridge 120 facilitates heterogeneousin-package integration by connecting the at least three semiconductordies 110 using an ultra-high density interconnect to conductively couplethe at least three semiconductor dies 110. The multi-die interconnectbridge 120 enables the integration, placement, or positioning of thecontact elements 112 near the edges of the at least three semiconductordies 110 due to the overall reduction in input/output (I/O). Thisgeometry facilitates precise physical coupling of the at least threesemiconductor dies 110 and results in the shortest possiblecommunication paths 122 between the at least three semiconductor dies110. The shortened communication paths 122 result in reduced loading onthe driving buffer, improving performance relative to other solutionssuch as silicon interposers where greatly increased communication pathlengths increase loading on the driving buffer, hindering performance.

In embodiments, the multi-die interconnect bridge 120 may include anynumber and/or combination of contact elements (lands, pads, grooves,sockets, etc.) to accept the insertion of one or more active elements(not depicted in FIGS. 1A and 1B). In embodiments, such active elementsmay be disposed such that communication between any one of the at leastthree semiconductor dies and any other of the at least threesemiconductor dies coupled to the multi-die interconnect bridge 120passes through the active element. In other embodiments, such activeelements may be disposed such that communication between selected onesof the at least three semiconductor dies 110 pass through the activeelement while communication between the remaining at least threesemiconductor dies 110 does not pass through the active element. Exampleactive elements include, but are not limited to, silicon dies thatinclude: control circuitry and/or repeater circuitry.

The multi-die interconnect bridge 120 may be fabricated using one ormore dielectric or electrically insulative materials. In someembodiments, the multi-die interconnect bridge 120 may be fabricated asa silicon die. In some embodiments, the multi-die interconnect bridge120 may be fabricated as a structure or member containing one or moreconductive layers and one or more dielectric layers. In someembodiments, the communication paths 122 through the multi-dieinterconnect bridge 120 may include a number of patterned tracesdeposited using any currently available or future developed patterningand/or deposition process. The conductive elements 122 forming thecommunication paths 122 may include one or more metallic or non-metallicelectrically conductive materials. Example electrically conductivematerials include, but are not limited to: copper; alloys or compoundscontaining copper; aluminum; alloys or compounds containing aluminum;conductive polymers, and similar.

In embodiments, the area of the first surface 132 of the semiconductorpackage substrate 130 occupied by the multi-die interconnect bridge 120is less than the area of the first surface 132 of the semiconductorpackage substrate 130 occupied by the smallest of the at least threesemiconductor dies 110. Thus, unlike conventional silicon interposers,the multi-die interconnect bridge 120 is less prone to quality issuessuch as warpage and does not require the use of through silicon vias,simplifying the manufacturing process and reducing overall manufacturingcomplexity.

The at least three semiconductor dies 110 conductively couple to contactelements 174A-174 n (lands, pads, groves, pins, sockets,etc.—collectively, “contact elements 174”) disposed in, on, about, oracross all or a portion of the first surface 132 of the semiconductorpackage substrate 130. Conductive elements 172A-172 n conductivelycouple the contact elements 174 on the first surface 132 of thesemiconductor package substrate 130 to contact elements 176A-176 n(lands, pads, groves, pins, sockets, etc.—collectively, “contactelements 176”) disposed in, on, about, or across all or a portion of alower or second surface 134 of the semiconductor package substrate 130.The first surface 132 and the second surface 134 are transverselyopposed across the thickness of the semiconductor package substrate 130.

In embodiments, the multi-die interconnect bridge 120 may include asemiconductor die or similar pre-fabricated structure that is disposed,positioned, placed, or otherwise affixed to the semiconductor packagesubstrate 130 such that the upper surface of the multi-die interconnectbridge 120 is parallel to the first surface 132 of the semiconductorpackage substrate 130. In embodiments, the upper surface of themulti-die interconnect bridge 120 may be co-planar with the firstsurface 132 of the semiconductor package substrate 130. In otherembodiments, the upper surface of the multi-die interconnect bridge 120may project from or be recessed into the first surface 132 of thesemiconductor package substrate 130. In other embodiments, the multi-dieinterconnect bridge 120 may include one or more structures (conductors,vias, etc.) that are formed integral with the semiconductor packagesubstrate 130. In such embodiments, the upper surface of the multi-dieinterconnect bridge 120 may be coplanar with the first surface 132 ofthe semiconductor package substrate 130. In some embodiments, themulti-die interconnect bridge 120 may conductively couple to one or morecircuits and/or conductive elements 172 disposed in the semiconductorpackage substrate 130. In some embodiments, the multi-die interconnectbridge 120 may conductively couple to one or more of the contactelements 174 disposed on the upper surface 132 of the semiconductorpackage substrate 130 and/or contact elements 176 disposed on the lowersurface 134 of the semiconductor package substrate 130.

The semiconductor package substrate 130 may include any number and/orcombination of electronic components, semiconductor devices, and/orlogic elements formed into one or more circuits. In some embodiments,the semiconductor package substrate 130 may include any number ofinterleaved patterned conductive and dielectric layers. Any number ofconductive structures 170A-170 n (solder balls, solder bumps, clips,wires, etc.—collectively, “conductive structures 170”) may physicallyaffix and/or conductively couple the semiconductor package substrate toan underlying substrate 140, such as a printed circuit board,motherboard, daughterboard, or similar. In at least some embodiments,the substrate 140 may form all or a portion of a processor-basedelectronic device, such as a portable electronic device or smartphone.

FIG. 2A is a plan view of an illustrative semiconductor package 200 thatincludes four semiconductor dies 110A-110D, each having a respective PHYlayer transceiver 210A-210D (collectively, “transceivers 210”)conductively coupled to a single, centrally located, multi-dieinterconnect bridge 120, in accordance with at least one embodimentdescribed herein. FIG. 2B is a schematic view of the communicationpathways provided by the single, centrally located, multi-dieinterconnect bridge 120 as depicted in FIG. 2A, in accordance with atleast one embodiment described herein. As depicted in FIGS. 2A and 2B,using only a single PHY layer transceiver 210 on each of thesemiconductor dies 110, direct bidirectional communication paths122A-122F exist between a single semiconductor die 110A and theremaining semiconductor

In embodiments, the multi-die interconnect bridge 120 permits direct,bidirectional, communication between any two of the semiconductor dies110A-110D using only a single transceiver 210 on each die. Suchrepresents a significant reduction in die surface area dedicated totransceivers 210 over prior designs where each communication path 122between two semiconductor dies 110 required a separate transceiver oneach die. Thus, instead of a single transceiver as depicted in FIG. 2A,in a traditional multi-die semiconductor package arrangement,semiconductor die 110A would have a first transceiver to conductivelycouple to semiconductor die 110B and a second transceiver toconductively couple to semiconductor die 110C. The input/output contactsmay be disposed in a peripheral area 220A-220D of each of thesemiconductor dies 110A-110D.

FIG. 3 is a plan view of a system 300 that includes a semiconductorpackage 102 in which a total of nine semiconductor dies 110A-110I arecommunicably coupled together using only four multi-die interconnectbridges 120A-120D, in accordance with at least one embodiment describedherein. As depicted in FIG. 3 , each of the multi-die interconnectbridges 120A-120D conductively couples to four different semiconductordies 110. Thus, communication between any two of the nine semiconductordies 110 requires, at most, communication through only a singleintervening semiconductor die 110.

Using the configuration depicted in FIG. 3 , the systems and methodsdescribed herein provide communication between diagonally opposed dies110A and 110I using communication paths 122A and 122B that traverse onlytwo multi-die interconnect bridges 120A and 120D and a singleintervening semiconductor die 110E. Under more conventional bridgingarchitecture (shown as dashed lines in FIG. 3 ), interconnect bridgesonly conductively couple laterally (not diagonally) adjacentsemiconductor dies 110. Such an arrangement or architecture wouldrequire communication paths 320A, 320B, 320C, and 320D pass through atotal of eight (8) transceivers 322A-322H and cross three interveningsemiconductor dies, 110D, 110G, 110H. Thus, when compared to traditionalbridges that conductively couple semiconductor dies only laterally (asopposed to the current systems and methods that conductively couplesemiconductor dies laterally AND diagonally), the systems and methodsdescribed herein reduce power consumption, reduce latency, increaseavailable semiconductor die area, and improve performance whileaddressing a significant issue facing communication and performance inmulti-die semiconductor packages.

FIG. 4 is a plan view of a system 400 that includes a semiconductorpackage 102 in which a total of sixteen semiconductor dies 110A-110P arecommunicably coupled together using only five multi-die interconnectbridges 120A-120E, in accordance with at least one embodiment describedherein. As depicted in FIG. 4 , each of the multi-die interconnectbridges 120A-120E conductively couples to four different semiconductordies 110. Thus, communication between any two of the sixteensemiconductor dies 110 requires, at most, communication through only twointervening semiconductor dies 110.

For example, using the configuration depicted in FIG. 4 , the systemsand methods described herein provide communication between diagonallyopposed dies 110A and 110P using communication paths 122A, 122B, and122C that traverse three multi-die interconnect bridges (120A, 120C and120E) across two intervening semiconductor dies (110F and 110K). Undermore conventional bridging architecture (shown as dashed lines in FIG. 4), interconnect bridges only conductively couple laterally (notdiagonally) adjacent semiconductor dies 110. Such an arrangement orarchitecture would require six communication paths 420A-420F and passthrough a total of twelve transceivers 422A-422L and cross fiveintervening semiconductor dies (110E, 110I, 110M, 110N, and 110O). Thus,when compared to traditional bridges that conductively couplesemiconductor dies only laterally (as opposed to the current systems andmethods that conductively couple semiconductor dies laterally ANDdiagonally), the systems and methods described herein reduce powerconsumption, reduce latency, increase available semiconductor die area,and improve performance while addressing a significant issue facingcommunication and performance in multi-die semiconductor packages.

FIG. 5A is a plan view of an illustrative semiconductor package 500Ahaving a first non-conventional configuration that includes threerectangular semiconductor dies 110A-110C conductively coupled to asingle, triangular, multi-die interconnect bridge 120, in accordancewith at least one embodiment described herein.

FIG. 5B is a plan view of an illustrative semiconductor package 500Bhaving a second non-conventional configuration that includes fourrectangular semiconductor dies 110A-110C conductively coupled to asingle, cruciform, multi-die interconnect bridge 120, in accordance withat least one embodiment described herein.

FIG. 5C is a plan view of an illustrative semiconductor package 500Chaving a third non-conventional configuration that includes threetriangular semiconductor dies 110A-110C conductively coupled to asingle, triangular, multi-die interconnect bridge 120, in accordancewith at least one embodiment described herein.

FIG. 5D is a plan view of an illustrative semiconductor package 500Dhaving a fourth non-conventional configuration that includes sixtriangular semiconductor dies 110A-110F conductively coupled to a singlehexagonal multi-die interconnect bridge 120, in accordance with at leastone embodiment described herein.

FIG. 5E is a plan view of an illustrative semiconductor package 500Ehaving a fifth non-conventional configuration that includes foursemiconductor dies 110A-110D conductively coupled to a single cruciformmulti-die interconnect bridge 120, in accordance with at least oneembodiment described herein.

As depicted by the illustrative semiconductor package configurations inFIGS. 5A-5E, the systems and methods described herein are not limited toconventional geometries and are adaptable to a variety of semiconductordie shapes, sizes, and configurations. Similarly, the multi-dieinterconnect bridge 120 may have any shape, size, or physical geometrythat provides sufficient overlap with each of the semiconductor dies 110to permit the attachment of the semiconductor dies 110 to the multi-dieinterconnect bridge 120 via the conductive structures 154.

FIG. 6A is a plan view of an illustrative system 600 that includes asemiconductor package 102 in which a single multi-die interconnectbridge 120 that includes an active die 610 conductively couples foursemiconductor dies 110A-110D, in accordance with at least one embodimentdescribed herein. FIG. 6B is a cross sectional elevation of theillustrative semiconductor package 102 depicted in FIG. 6A along sectionline 6B-6B, in accordance with at least one embodiment described herein.In embodiments, the multi-die interconnect bridge 120 may include apassive electronic element. Passive electronic elements include, but arenot limited to, passive electrical components, such as conductors,resistors, inductors, capacitors, and similar. One or more activeelements, such as an active die 610, may be conductively coupled to themulti-die interconnect bridge 120. Such active dies 610 may includecircuitry such as controller circuitry, repeater circuitry, filtercircuitry, amplification circuitry, and similar. Power for the activedie 610 may be supplied by one or more semiconductor dies 110 via themulti-die interconnect bridge 120.

In at least some embodiments, one or more signals 620A may be suppliedby a first semiconductor die 110A to the multi-die interconnect bridge120. All or a portion of the signal may be provided as an input signal630 to the active die 610. The active die 610 may provide an outputsignal 640 to the multi-die interconnect bridge 120. The signal 620B maythen be provided, via the multi-die interconnect bridge 120, to a secondsemiconductor die 110B. For example, the first semiconductor die 110Amay generate a signal 620A that is provided to the multi-dieinterconnect bridge 120. One or more filters, that includes any numberand/or combination of passive elements such as resistors, capacitors,and/or inductors (LC-filter, RC-filter, RL-filter, RLC-filter, etc.) maybe formed in the multi-die interconnect bridge 120. The filtered signalforms an input signal 630 to an active repeater die 610. The higherenergy output signal 640 from the repeater die is conveyed, via themulti-die interconnect bridge 120, as an input signal 620A to the secondsemiconductor die 110B.

Although the active element 610 is depicted as conductively coupled tothe upper surface of the multi-die interconnect bridge 120, in otherembodiments, the active element 610 may be conductively coupled to theupper surface of the multi-die interconnect bridge 120, the lowersurface of the multi-die interconnect bridge 120, or any combinationthereof

FIG. 7 is a schematic diagram of an illustrative electronic device 700that includes a system-in-chip (SiC) 102 that includes a multi-dieinterconnect bridge 120 as described in FIGS. 1 through 6 conductivelycoupling a graphical processing unit 710, processor circuitry 712, andsystem memory 740, and in accordance with at least one embodimentdescribed herein. The following discussion provides a brief, generaldescription of the components forming the illustrative electronic device702 such as a smartphone, wearable computing device, portable computingdevice, or any similar device having at least one system-in-chip 102that includes a multi-die interconnect bridge 120. In embodiments, themulti-die interconnect bridge 120 may be partially or completelydisposed in the substrate 130 to which the graphical processing unit710, processor circuitry 712, and system memory 740 are operably coupledand physically affixed.

The electronic device 702 includes processor circuitry 712 capable ofexecuting machine-readable instruction sets 714, reading data and/orinstructions 714 from one or more storage devices 760 and writing datato the one or more storage devices 760. Those skilled in the relevantart will appreciate that the illustrated embodiments as well as otherembodiments can be practiced with other circuit-based deviceconfigurations, including portable electronic or handheld electronicdevices, for instance smartphones, portable computers, wearablecomputers, microprocessor-based or programmable consumer electronics,personal computers (“PCs”), network PCs, minicomputers, mainframecomputers, and the like.

The processor circuitry 712 may include any number of hardwired orconfigurable circuits, some or all of which may include programmableand/or configurable combinations of electronic components, semiconductordevices, and/or logic elements that are disposed partially or wholly ina PC, server, or other computing system capable of executingprocessor-readable instructions.

The electronic device 702 includes a bus or similar communications link716 that communicably couples and facilitates the exchange ofinformation and/or data between various system components including theSiC 102, one or more wireless I/O interfaces 720, one or more wired I/Ointerfaces 730, one or more storage devices 760, and/or one or morenetwork interfaces 770. The electronic device 702 may be referred to inthe singular herein, but this is not intended to limit the embodimentsto a single electronic device and/or system, since in certainembodiments, there may be more than one electronic device 702 thatincorporates, includes, or contains any number of communicably coupled,collocated, or remote networked circuits or devices.

The SiC 102 includes a multi-die interconnect bridge 120 communicablycoupling the graphics processing unit 710, the processor circuitry 712,and the system memory 740. In embodiments, a greater or lesser number ofcomponents may be included in the SiC 102. The graphics processing unit(“GPU”) 710 may include any number and/or combination of systems and/ordevices capable of generating a video output signal at a wired orwireless video output interface 711.

The processor circuitry 712 may include any number, type, or combinationof devices. At times, the processor circuitry 712 may be implemented inwhole or in part in the form of semiconductor devices such as diodes,transistors, inductors, capacitors, and resistors. Such animplementation may include, but is not limited to any current or futuredeveloped single- or multi-core processor or microprocessor, such as: onor more systems on a chip (SOCs); central processing units (CPUs);digital signal processors (DSPs); graphics processing units (GPUs);application-specific integrated circuits (ASICs), programmable logicunits, field programmable gate arrays (FPGAs), and the like. Unlessdescribed otherwise, the construction and operation of the variousblocks shown in FIG. 7 are of conventional design. Consequently, suchblocks need not be described in further detail herein, as they will beunderstood by those skilled in the relevant art. The bus 716 thatinterconnects at least some of the components of the electronic device702 may employ any known serial or parallel bus structures orarchitectures.

The system memory 740 may include read-only memory (“ROM”) 742 andrandom access memory (“RAM”) 746. A portion of the ROM 742 may be usedto store or otherwise retain a basic input/output system (“BIOS”) 744.The BIOS 744 provides basic functionality to the electronic device 702,for example by causing the processor circuitry 712 to load one or moremachine-readable instruction sets 714. In embodiments, at least some ofthe one or more machine-readable instruction sets 714 cause at least aportion of the processor circuitry 712 to provide, create, produce,transition, and/or function as a dedicated, specific, and particularmachine, for example a word processing machine, a digital imageacquisition machine, a media playing machine, a gaming system, acommunications device, or similar.

The electronic device 702 may include at least one wireless input/output(I/O) interface 720. The at least one wireless I/O interface 720 may becommunicably coupled to one or more physical output devices 722 (tactiledevices, video displays, audio output devices, hardcopy output devices,etc.). The at least one wireless I/O interface 720 may communicablycouple to one or more physical input devices 724 (pointing devices,touchscreens, keyboards, tactile devices, etc.). The at least onewireless I/O interface 720 may include any currently available or futuredeveloped wireless I/O interface. Example wireless I/O interfacesinclude, but are not limited to: BLUETOOTH®, near field communication(NFC), and similar.

The electronic device 702 may include one or more wired input/output(I/O) interfaces 730. The at least one wired I/O interface 730 may becommunicably coupled to one or more physical output devices 722 (tactiledevices, video displays, audio output devices, hardcopy output devices,etc.). The at least one wired I/O interface 730 may be communicablycoupled to one or more physical input devices 724 (pointing devices,touchscreens, keyboards, tactile devices, etc.). The wired I/O interface730 may include any currently available or future developed I/Ointerface. Example wired I/O interfaces include, but are not limited to:universal serial bus (USB) and similar.

The electronic device 702 may include one or more communicably coupled,non-transitory, data storage devices 760. The data storage devices 760may include one or more hard disk drives and/or one or more solid-statestorage devices. The one or more data storage devices 760 may includeany current or future developed storage appliances, network storagedevices, and/or systems. Non-limiting examples of such data storagedevices 760 may include, but are not limited to, any current or futuredeveloped non-transitory storage appliances or devices, such as one ormore magnetic storage devices, one or more optical storage devices, oneor more electro-resistive storage devices, one or more molecular storagedevices, one or more quantum storage devices, or various combinationsthereof In some implementations, the one or more data storage devices760 may include one or more removable storage devices, such as one ormore flash drives, flash memories, flash storage units, or similarappliances or devices capable of communicable coupling to and decouplingfrom the electronic device 702.

The one or more data storage devices 760 may include interfaces orcontrollers (not shown) communicatively coupling the respective storagedevice or system to the bus 716. The one or more data storage devices760 may store, retain, or otherwise contain machine-readable instructionsets, data structures, program modules, data stores, databases, logicalstructures, and/or other data useful to the processor circuitry 712and/or one or more applications executed on or by the processorcircuitry 712. In some instances, one or more data storage devices 760may be communicably coupled to the processor circuitry 712, for examplevia the bus 716 or via one or more wired communications interfaces 730(e.g., Universal Serial Bus or USB); one or more wireless communicationsinterfaces 720 (e.g., Bluetooth®, Near Field Communication or NFC);and/or one or more network interfaces 770 (IEEE 802.3 or Ethernet, IEEE802.11, or WiFi®, etc.).

Processor-readable instruction sets 714 and other programs,applications, logic sets, and/or modules may be stored in whole or inpart in the system memory 740. Such instruction sets 714 may betransferred, in whole or in part, from the one or more data storagedevices 760. The instruction sets 714 may be loaded, stored, orotherwise retained in system memory 740, in whole or in part, duringexecution by the processor circuitry 712. The processor-readableinstruction sets 714 may include machine-readable and/orprocessor-readable code, instructions, or similar logic capable ofproviding the speech coaching functions and capabilities describedherein.

The electronic device 702 may include power management circuitry 750that controls one or more operational aspects of the energy storagedevice 752. In embodiments, the energy storage device 752 may includeone or more primary (i.e., non-rechargeable) or secondary (i.e.,rechargeable) batteries or similar energy storage devices. Inembodiments, the energy storage device 752 may include one or moresupercapacitors or ultracapacitors. In embodiments, the power managementcircuitry 750 may alter, adjust, or control the flow of energy from anexternal power source 754 to the energy storage device 752 and/or to theelectronic device 702. The power source 754 may include, but is notlimited to, a solar power system, a commercial electric grid, a portablegenerator, an external energy storage device, or any combinationthereof.

For convenience, the SiC 102, the wireless I/O interface 720, the wiredI/O interface 730, the power management circuitry 750, the storagedevice 760, and the network interface 770 are illustrated ascommunicatively coupled to each other via the bus 716, thereby providingconnectivity between the above-described components. In alternativeembodiments, the above-described components may be communicativelycoupled in a different manner than illustrated in FIG. 7 . For example,one or more of the above-described components may be directly coupled toother components, or may be coupled to each other, via one or moreintermediary components (not shown). In another example, one or more ofthe above-described components may be integrated into the SiC 102 andcommunicably coupled to other components via the multi-die interconnectbridge 120. In some embodiments, all or a portion of the bus 716 may beomitted and the components are coupled directly to each other usingsuitable wired or wireless connections.

FIG. 8 is a high-level flow diagram of an illustrative method 800 offabricating a semiconductor package 102, such as a system-in-chip, thatincorporates at least one multi-die interconnect bridge 120 thatcommunicably couples at least three semiconductor dies 110, inaccordance with at least one embodiment described herein. The multi-dieinterconnect bridge 120 may be at least partially embedded or otherwiseincorporated into the semiconductor package substrate 130. The multi-dieinterconnect bridge 120 conductively couples each of the at least threesemiconductor dies 110 to each of the remaining semiconductor dies 110,beneficially providing the physically shortest distance between each ofthe semiconductor dies 110. In embodiments, the multi-die interconnectbridge 120 is a passive bridge (i.e., a bridge that contains nointrinsic active components) formed in, on, or about a silicon die. Inembodiments, the multi-die interconnect bridge 120 may be fabricatedindependent of the semiconductor package 102 and may be incorporatedinto the semiconductor package substrate 130 during the packagefabrication or assembly process. The method 800 commences at 802.

At 804, a multi-die interconnect bridge 120 is disposed, positioned,patterned, or otherwise affixed, bonded or attached to, deposited on, orat least partially embedded in a first surface of a semiconductorpackage substrate 130. In embodiments, the multi-die interconnect bridge120 may include any number and/or combination of passive elements(conductors, resistors, capacitors, inductors, etc.) disposed a silicondie. In embodiments, the multi-die interconnect bridge 120 may includeany number and/or combination of passive elements formed integrally in,on, across, or about the semiconductor package substrate 130. Inembodiments, the multi-die interconnect bridge 120 may include anynumber and/or combination of passive elements disposed as a single or asmultiple layers in a layered dielectric structure such as a circuitboard.

In some embodiments, the multi-die interconnect bridge 120 may bedisposed in a recessed region formed on the first surface 132 of thesemiconductor package substrate 130. In such embodiments, the uppersurface of the multi-die interconnect bridge 120 may project above thefirst surface 132, may be recessed below the first surface 132, or maybe coplanar with the first surface 132 of the semiconductor packagesubstrate 130. In some embodiments, the multi-die interconnect bridge120 may be physically affixed, for example via chemical bonding, to thefirst surface 132 of the semiconductor package substrate 130.

The multi-die interconnect bridge 120 may have any physical geometry,size, and/or shape. For example, the multi-die interconnect bridge 120may have a rectangular, circular, oval, triangular, polygonal, ortrapezoidal physical geometry. The multi-die interconnect bridge 120 mayhave any thickness, longitudinal, and lateral dimensions. In at leastsome embodiments, the physical geometry, thickness, lateral dimensionand longitudinal dimension of the multi-die interconnect bridge 120 maybe based, at least in part, on the physical size, shape, and/or theconfiguration of the contact elements 112A-112 n proximate the multi-dieinterconnect bridge 120 and disposed on the exterior of thesemiconductor dies 110. In embodiments, the multi-die interconnectbridge 120 may conductively couple each of the at least threesemiconductor dies 110 to each of the remaining at least threesemiconductor dies 110. In other embodiments, the multi-die interconnectbridge 120 may selectively conductively couple each of some or all ofthe at least three semiconductor dies 110 to each of at least some ofthe remaining at least three semiconductor dies 110.

At 806, at least three semiconductor dies 110 are conductively coupledto the multi-die interconnect bridge 120. In embodiments, each of thesemiconductor dies 110 may have a plurality of contact elements 112patterned, deposited, formed, or otherwise disposed in, on, about oracross at least a portion of the external surface of the respectivesemiconductor die 110. Conductive structures, including solder balls 152and/or solder bumps 154 may be conductively coupled to some or all ofthe contact elements 112. In at least some embodiments, at least some ofthe conductive structures (e.g., solder bumps 154) may be reflowed toconductively couple the semiconductor die 110 to the multi-dieinterconnect bridge 120. In at least some embodiments, at least some ofthe conductive structures (e.g., solder balls 152) may be reflowed toconductively couple the semiconductor die 110 to the semiconductorpackage substrate 130. In embodiments, other conductive coupling methodsmay be used to conductively couple the semiconductor dies 110 to themulti-die interconnect bridge 120.

The multi-die interconnect bridge 120 occupies a first area on the firstsurface 132 of the semiconductor package substrate 130. The smallest ofthe at least three semiconductor dies 110 occupies a second area on thefirst surface 132 of the semiconductor package substrate 130. Inembodiments the first area (occupied by the multi-die interconnectbridge 120) is less than the second area (occupied by the smallest ofthe at least three semiconductor dies 110). The method 800 concludes at808.

FIG. 9 is a high-level flow diagram of an illustrative method 900 ofconductively coupling one or more active dies 610 to a passive multi-dieinterconnect bridge 120, in accordance with at least one embodimentdescribed herein. The method 900 may be used in conjunction with themethod 800 discussed above with regard to FIG. 8 . In embodiments, oneor more active dies 610, such as one or more dies containing controlcircuitry and/or repeater circuitry, may be conductively coupled to apassive multi-die interconnect bridge 120 to provide additionalfunctionality. The method 900 commences at 902.

At 904, an active die 610 (i.e., a die that includes at least one activeelectronic and/or semiconductor component) is conductively coupled tothe multi-die interconnect bridge 120. In embodiments, at least aportion of the communication paths 122 through the multi-dieinterconnect bridge 120 pass through the active die 610. In otherembodiments, signals passing between selected semiconductor dies 110pass through the active die 610. For example, semiconductor dies 110A,110B, and 110C are conductively coupled to the multi-die interconnectbridge 120. The communication path 122A-B between dies 110A and 110Bpass through an active die 610 coupled to the multi-die interconnectbridge 120 while the communication path 122A-C between dies 110A and110C and the communication path 122B-C between 110B and 110C arecommunicated via the multi-die interconnect bridge 120 but do not passthrough the active die 610. In other embodiments, all of thecommunication paths 122 through the multi-die interconnect bridge 120pass through the active die 610. The method 900 concludes at 912.

While FIGS. 8 and 9 illustrate various operations according to one ormore embodiments, it is to be understood that not all of the operationsdepicted in FIGS. 8 and 9 are necessary for other embodiments. Indeed,it is fully contemplated herein that in other embodiments of the presentdisclosure, the operations depicted in FIGS. 8 and 9 , and/or otheroperations described herein, may be combined in a manner notspecifically shown in any of the drawings, but still fully consistentwith the present disclosure. Thus, claims directed to features and/oroperations that are not exactly shown in one drawing are deemed withinthe scope and content of the present disclosure.

As used in this application and in the claims, a list of items joined bythe term “and/or” can mean any combination of the listed items. Forexample, the phrase “A, B and/or C” can mean A; B; C; A and B; A and C;B and C; or A, B and C. As used in this application and in the claims, alist of items joined by the term “at least one of” can mean anycombination of the listed terms. For example, the phrases “at least oneof A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B andC.

Any of the operations described herein may be implemented in a systemthat includes one or more mediums (e.g., non-transitory storage mediums)having stored therein, individually or in combination, instructions thatwhen executed by one or more processors perform the methods. Here, theprocessor may include, for example, a server CPU, a mobile device CPU,and/or other programmable circuitry. Also, it is intended thatoperations described herein may be distributed across a plurality ofphysical devices, such as processing structures at more than onedifferent physical location. The storage medium may include any type oftangible medium, for example, any type of disk including hard disks,floppy disks, optical disks, compact disk read-only memories (CD-ROMs),rewritable compact disks (CD-RWs), and magneto-optical disks,semiconductor devices such as read-only memories (ROMs), random accessmemories (RAMs) such as dynamic and static RAMs, erasable programmableread-only memories (EPROMs), electrically erasable programmableread-only memories (EEPROMs), flash memories, Solid State Disks (SSDs),embedded multimedia cards (eMMCs), secure digital input/output (SDIO)cards, magnetic or optical cards, or any type of media suitable forstoring electronic instructions. Other embodiments may be implemented assoftware executed by a programmable control device.

Thus, the present disclosure is directed to systems and methods ofconductively coupling at least three semiconductor dies included in asemiconductor package using a multi-die interconnect bridge that isembedded, disposed, or otherwise integrated into the semiconductorpackage substrate. The multi-die interconnect bridge is a passive devicethat includes passive electronic components such as conductors,resistors, capacitors and inductors. The multi-die interconnect bridgecommunicably couples each of the semiconductor dies included in the atleast three semiconductor dies to each of at least some of the remainingat least three semiconductor dies. An active silicon die, such as asilicon die containing control circuitry and/or repeater circuitry maybe coupled to the multi-die interconnect bridge to provide additionalfunctionality. The multi-die interconnect bridge occupies a first areaon the surface of the semiconductor package substrate. The smallest ofthe at least three semiconductor dies coupled to the multi-dieinterconnect bridge 120 occupies a second area on the surface of thesemiconductor package substrate, where the second area is greater thanthe first area.

The following examples pertain to further embodiments. The followingexamples of the present disclosure may comprise subject material such asat least one device, a method, at least one machine-readable medium forstoring instructions that when executed cause a machine to perform actsbased on the method, means for performing acts based on the methodand/or a system for providing an externally accessible test wirebond ina semiconductor package mounted on a substrate.

According to example 1, there is provided a semiconductor package. Thesemiconductor package includes: a semiconductor package substrate havinga first surface and a transversely opposed second surface separated by athickness; at least three semiconductor dies coupled to thesemiconductor package substrate; where a smallest of the at least threesemiconductor dies occupies a first physical area on the first surfaceof the semiconductor package substrate; and a multi-die interconnectbridge that includes one or more conductive members disposed proximatethe first surface of the semiconductor package substrate and occupying asecond physical area of the first surface of the semiconductor packagesubstrate; wherein the multi-die interconnect bridge conductivelycouples each of the at least three semiconductor dies to each of theremaining at least three semiconductor dies; and wherein the secondphysical area occupied by the multi-die interconnect bridge is less thanthe first physical area of a smallest of the at least threesemiconductor dies.

Example 2 may include elements of example 1 where the one or moreconductive members included in the multi-die interconnect bridgeconductively couple the at least three semiconductor dies withoutpassing through any intervening semiconductor die included in the atleast three silicon dies.

Example 3 may include elements of any of examples 1 and 2, and thesemiconductor package may additionally include an active diecommunicably coupled to the multi-die interconnect bridge.

Example 4 may include elements of any of examples 1 through 3 where theactive die comprises control circuitry.

Example 5 may include elements of any of examples 1 through 4 where theactive die comprises a repeater die.

Example 6 may include elements of any of examples 1 through 5 where themulti-die interconnect bridge defines a shortest distance between eachof the at least three semiconductor dies and the remaining at leastthree semiconductor dies.

Example 7 may include elements of any of examples 1 through 6 where themulti-die interconnect bridge comprises a silicon die embedded at leastpartially in the first surface of the semiconductor package substrate.

Example 8 may include elements of any of examples 1 through 7 where themulti-die interconnect bridge comprises a silicon bridge formed integralwith the semiconductor package substrate.

According to example 9 there is provided a semiconductor packagefabrication method, comprising disposing a multi-die interconnect bridgethat includes a plurality of conductive members proximate a firstsurface of a semiconductor package substrate, the multi-die interconnectbridge occupying a first physical area of the first surface of thesemiconductor package substrate; and conductively coupling each of atleast three semiconductor dies to the multi-die interconnect bridge suchthat the plurality of conductive members conductively couples each ofthe at least three semiconductor dies to the remaining at least threesemiconductor dies; where a smallest of the at least three semiconductordies occupies a second physical area on the first surface of thesemiconductor package substrate; and where the first physical areaoccupied by the multi-die interconnect bridge is less than the secondphysical area of a smallest of the at least three semiconductor dies.

Example 10 may include elements of example 9 where forming a multi-dieinterconnect bridge that includes a plurality of conductive membersproximate a first surface of a semiconductor package substrate furthercomprises: forming a multi-die interconnect bridge that includes aplurality of conductive members proximate a first surface of asemiconductor package substrate such that the plurality of conductivemembers included in the multi-die interconnect bridge conductivelycouple the at least three semiconductor dies without passing through anyintervening semiconductor die included in the at least three silicondies.

Example 11 may include elements of any of examples 9 or 10 and themethod may additionally include: conductively coupling at least oneactive semiconductor die to the multi-die interconnect bridge.

Example 12 may include elements of any of examples 9 through 11 whereconductively coupling at least one active semiconductor die to themulti-die interconnect bridge may include: conductively coupling atleast one active semiconductor die that includes control circuitry tothe multi-die interconnect bridge.

Example 13 may include elements of any of examples 9 through 12 whereconductively coupling at least one active semiconductor die to themulti-die interconnect bridge may include: conductively coupling atleast one active semiconductor die that includes a repeater die to themulti-die interconnect bridge.

Example 14 may include elements of any of examples 9 through 13 whereconductively coupling each of at least three semiconductor dies to themulti-die interconnect bridge further comprises: conductively couplingeach of at least three semiconductor dies to the multi-die interconnectbridge that defines a shortest distance between each of the at leastthree semiconductor dies and the remaining at least three semiconductordies.

Example 15 may include elements of any of examples 9 through 14 wheredisposing a multi-die interconnect bridge that includes a plurality ofconductive members proximate a first surface of a semiconductor packagesubstrate may include: at least partially embedding a silicon die in thefirst surface of the semiconductor package substrate to provide themulti-die interconnect bridge.

Example 16 may include elements of any of examples 9 through 15 wheredisposing a multi-die interconnect bridge that includes a plurality ofconductive members proximate a first surface of a semiconductor packagesubstrate may include: forming an integral silicon bridge in thethickness of the semiconductor package substrate.

According to example 17 there is provided a semiconductor packagefabrication system. The system may include: means for disposing amulti-die interconnect bridge that includes a plurality of conductivemembers proximate a first surface of a semiconductor package substrate,the multi-die interconnect bridge occupying a first physical area of thefirst surface of the semiconductor package substrate; and means forconductively coupling each of at least three semiconductor dies to themulti-die interconnect bridge such that the plurality of conductivemembers conductively couples each of the at least three semiconductordies to the remaining at least three semiconductor dies; where asmallest of the at least three semiconductor dies occupies a secondphysical area on the first surface of the semiconductor packagesubstrate; and where the first physical area occupied by the multi-dieinterconnect bridge is less than the second physical area of a smallestof the at least three semiconductor dies.

Example 18 may include elements of example 17 where the means forforming a multi-die interconnect bridge that includes a plurality ofconductive members proximate a first surface of a semiconductor packagesubstrate may further include: means for forming a multi-dieinterconnect bridge that includes a plurality of conductive membersproximate a first surface of a semiconductor package substrate such thatthe plurality of conductive members included in the multi-dieinterconnect bridge conductively couple the at least three semiconductordies without passing through any intervening semiconductor die includedin the at least three silicon dies.

Example 19 may include elements of any of examples 17 or 18 and thesystem may further include: means for conductively coupling at least oneactive semiconductor die to the multi-die interconnect bridge.

Example 20 may include elements of any of examples 17 through 19 wherethe means for conductively coupling at least one active semiconductordie to the multi-die interconnect bridge may include: means forconductively coupling at least one active semiconductor die thatincludes control circuitry to the multi-die interconnect bridge.

Example 21 may include elements of any of examples 17 through 20 wherethe means for conductively coupling at least one active semiconductordie to the multi-die interconnect bridge may include: means forconductively coupling at least one active semiconductor die thatincludes a repeater die to the multi-die interconnect bridge.

Example 22 may include elements of any of examples 17 through 21 wherethe means for conductively coupling each of at least three semiconductordies to the multi-die interconnect bridge may further include: means forconductively coupling each of at least three semiconductor dies to themulti-die interconnect bridge that defines a shortest distance betweeneach of the at least three semiconductor dies and the remaining at leastthree semiconductor dies.

Example 23 may include elements of any of examples 17 through 22 wherethe means for disposing a multi-die interconnect bridge that includes aplurality of conductive members proximate a first surface of asemiconductor package substrate may include: means for at leastpartially embedding a silicon die in the first surface of thesemiconductor package substrate to provide the multi-die interconnectbridge.

Example 24 may include elements of any of examples 17 through 23 wherethe means for disposing a multi-die interconnect bridge that includes aplurality of conductive members proximate a first surface of asemiconductor package substrate may include: means for forming anintegral silicon bridge in the thickness of the semiconductor packagesubstrate.

According to example 25 there is provided an electronic device. Theelectronic device may include: a printed circuit board; a semiconductorpackage conductively coupled to the printed circuit board, thesemiconductor package including: a semiconductor package substratecoupled to the printed circuit board, the semiconductor packagesubstrate having a first surface and a transversely opposed secondsurface separated by a thickness; at least three semiconductor diesincluded in the semiconductor package and coupled to the first surfaceof the semiconductor package substrate; where a smallest of the at leastthree semiconductor dies occupies a first physical area on the firstsurface of the semiconductor package substrate; and a multi-dieinterconnect bridge disposed proximate the first surface of thesemiconductor package substrate, the multi-die interconnect bridgeincluding one or more conductive members and occupying a second physicalarea of the first surface of the semiconductor package substrate; wherethe multi-die interconnect bridge conductively couples each of the atleast three semiconductor dies to each of the remaining at least threesemiconductor dies; and where the second physical area occupied by themulti-die interconnect bridge is less than the first physical area of asmallest of the at least three semiconductor dies.

Example 26 may include elements of example 25 where the one or moreconductive members included in the multi-die interconnect bridgeconductively couple the at least three semiconductor dies withoutpassing through any intervening semiconductor die included in the atleast three silicon dies.

Example 27 may include elements of any of examples 25 or 26 where thesemiconductor package further includes an active die communicablycoupled to the multi-die interconnect bridge.

Example 28 may include elements of any of examples 25 through 27 wherethe active die comprises control circuitry.

Example 29 may include elements of any of examples 25 through 28 wherethe active die comprises repeater circuitry.

Example 30 may include elements of any of examples 25 through 29 wherethe silicon bridge defines a shortest distance between each of the atleast three semiconductor dies and the remaining at least threesemiconductor dies.

Example 31 may include elements of any of examples 25 through 30 wherethe multi-die interconnect bridge comprises a silicon die embedded atleast partially in the first surface of the semiconductor packagesubstrate.

Example 32 may include elements of any of examples 25 through 31 wherethe multi-die interconnect bridge comprises a silicon bridge formedintegral with the semiconductor package substrate.

The terms and expressions which have been employed herein are used asterms of description and not of limitation, and there is no intention,in the use of such terms and expressions, of excluding any equivalentsof the features shown and described (or portions thereof), and it isrecognized that various modifications are possible within the scope ofthe claims. Accordingly, the claims are intended to cover all suchequivalents.

What is claimed:
 1. A semiconductor package, comprising: a packagesubstrate; a multi-die interconnect bridge coupled to the packagesubstrate; a first die over a first portion of the package substrate andover a first portion of the multi-die interconnect bridge, the first dieelectrically coupled to the multi-die interconnect bridge; a second dieover a second portion of the package substrate and over a second portionof the multi-die interconnect bridge, the second die electricallycoupled to the multi-die interconnect bridge; a third die over a thirdportion of the package substrate and over a third portion of themulti-die interconnect bridge, the third die electrically coupled to themulti-die interconnect bridge, the third die diagonally opposed to thefirst die across the multi-die interconnect bridge, and the third diedirectly electrically connected to the first die by the multi-dieinterconnect bridge; and a fourth die over a fourth portion of thepackage substrate and over a fourth portion of the multi-dieinterconnect bridge, the fourth die electrically coupled to themulti-die interconnect bridge.
 2. The semiconductor package of claim 1,wherein the first die is directly electrically connected to the seconddie by the multi-die interconnect bridge.
 3. The semiconductor packageof claim 2, wherein the first die is directly electrically connected tothe fourth die by the multi-die interconnect bridge.
 4. Thesemiconductor package of claim 1, wherein the fourth die is diagonallyopposed to the second die across the multi-die interconnect bridge, andthe fourth die is directly electrically connected to the second die bythe multi-die interconnect bridge.
 5. The semiconductor package of claim1, wherein the first die and the third die have a same size.
 6. Thesemiconductor package of claim 1, wherein the first die and the thirddie have different sizes from one another.
 7. The semiconductor packageof claim 1, wherein the first die, the second die, the third die and thefourth die all have a same size.
 8. The semiconductor package of claim1, wherein the first die, the second die, the third die and the fourthdie have different sizes from one another.
 9. The semiconductor packageof claim 1, further comprising: a second multi-die interconnect bridgecoupled to the package substrate, the second multi-die interconnectbridge coupled to the first die and the second die.
 10. Thesemiconductor package of claim 1, wherein the first die, the second die,the third die and the fourth die are coupled to a first side of thepackage substrate, the semiconductor package further comprising: aplurality of bumps coupled to a second side of the package substrate,the second side opposite the first side.
 11. A method of fabricating asemiconductor package, the method comprising: coupling a multi-dieinterconnect bridge to a package substrate; electrically coupling afirst die to the multi-die interconnect bridge, the first die over afirst portion of the package substrate and over a first portion of themulti-die interconnect bridge; electrically coupling a first die to themulti-die interconnect bridge, the second die over a second portion ofthe package substrate and over a second portion of the multi-dieinterconnect bridge; electrically coupling a first die to the multi-dieinterconnect bridge, the third die over a third portion of the packagesubstrate and over a third portion of the multi-die interconnect bridge,the third die diagonally opposed to the first die across the multi-dieinterconnect bridge, and the third die directly electrically connectedto the first die by the multi-die interconnect bridge; and electricallycoupling a first die to the multi-die interconnect bridge, the fourthdie over a fourth portion of the package substrate and over a fourthportion of the multi-die interconnect bridge.
 12. The method of claim11, wherein the first die is directly electrically connected to thesecond die by the multi-die interconnect bridge.
 13. The method of claim12, wherein the first die is directly electrically connected to thefourth die by the multi-die interconnect bridge.
 14. The method of claim11, wherein the fourth die is diagonally opposed to the second dieacross the multi-die interconnect bridge, and the fourth die is directlyelectrically connected to the second die by the multi-die interconnectbridge.
 15. The method of claim 11, further comprising: coupling asecond multi-die interconnect bridge to the package substrate, thesecond multi-die interconnect bridge coupled to the first die and thesecond die.
 16. The method of claim 11, wherein the first die, thesecond die, the third die and the fourth die are coupled to a first sideof the package substrate, the method further comprising: coupling aplurality of bumps to a second side of the package substrate, the secondside opposite the first side.
 17. An electronic device, comprising: aprinted circuit board; and a semiconductor package coupled to thecircuit board, the semiconductor package comprising” a packagesubstrate; a multi-die interconnect bridge coupled to the packagesubstrate; a first die over a first portion of the package substrate andover a first portion of the multi-die interconnect bridge, the first dieelectrically coupled to the multi-die interconnect bridge; a second dieover a second portion of the package substrate and over a second portionof the multi-die interconnect bridge, the second die electricallycoupled to the multi-die interconnect bridge; a third die over a thirdportion of the package substrate and over a third portion of themulti-die interconnect bridge, the third die electrically coupled to themulti-die interconnect bridge, the third die diagonally opposed to thefirst die across the multi-die interconnect bridge, and the third diedirectly electrically connected to the first die by the multi-dieinterconnect bridge; a fourth die over a fourth portion of the packagesubstrate and over a fourth portion of the multi-die interconnectbridge, the fourth die electrically coupled to the multi-dieinterconnect bridge, wherein the first die, the second die, the thirddie and the fourth die are coupled to a first side of the packagesubstrate; and a plurality of bumps coupled to a second side of thepackage substrate, the second side opposite the first side, theplurality of bumps electrically coupled to the printed circuit board.18. The electronic device of claim 17, wherein the first die is directlyelectrically connected to the second die by the multi-die interconnectbridge.
 19. The electronic device of claim 18, wherein the first die isdirectly electrically connected to the fourth die by the multi-dieinterconnect bridge.
 20. The electronic device of claim 17, wherein thefourth die is diagonally opposed to the second die across the multi-dieinterconnect bridge, and the fourth die is directly electricallyconnected to the second die by the multi-die interconnect bridge.